A New Modified Reducible Complexity Hardware Efficient FIR Filter by Using Proposed Shift and Adder Architectures

Finite-impulse response (FIR) Filter is widely used in wireless sensor networks as a signal pre-processing step. Because sensor nodes require a long working periods and ultra-low cost, traditional FIR structures are inapplicable as multipliers occupy too much die size for such node’s chips. This paper proposes novel FIR filter structures used in the design of application specific integrated circuits (ASICs) for sensor nodes, and to add with again my project includes reconfigurable FIR filters using CSM and PSM which can reduce the hardware cost to a minimum by giving reconfig. ability and reduce the complexity. The experiments show that the proposed FIR structure can lead to significant hardware savings from the traditional FIR filter. This architecture as the capacity to operate over varies word length coefficient of the filter. also, it easy to prove that this will offer good area, improved speed & power reduction than the existing one.